In the emerging fields of nano- and molecular electronics a strong need for nano-electrodes arises from the
wish to be able to contact single nano-objects such as quantum dots (QDs) or molecules. There are different methods
known from literature how to fabricate such electrodes, for example electromigration, mechanically controllable break
junctions, or scanning probe techniques, all of which have their specific advantages and drawbacks. In this talk we will
use a scheme of controlled electrochemical deposition which features the following benefits: the electrodes are stable,
no islands are unintentionally created during the fabrication process, and it is relatively straight forward to implement a
third electrode acting as gate.
In our experiments we start with a pair of gold electrodes separated by a 200 nm gap (Fig. 2 (a)) prepared by
electron beam lithography (EBL). These electrodes are immersed into a solution of KI and I₂ in ethanol which has been
saturated by dissolving gold in it [1]. Gold covered glass sheets are used as counter and reference electrodes. For the
deposition both nano-electrodes are connected to the same DC potential, while a voltage is either applied directly to the
counter electrode or a potentiostat setup is used. Additionally an AC voltage is applied between the two nano-electrodes
which allows us to in-situ monitor the conductance with a lock-in amplifier (see Fig. 1).
When the sample is immersed into the solution, the conductance rises due to ionic currents. For the deposition
a voltage of typically 60 mV is applied to the counter electrode with respect to the working electrodes. The conductance
is recorded until it reaches a threshold value at which the deposition is stopped. After deposition the gap between the
two electrodes is clearly below 10 nm, as conductance measurements after rinsing and drying as well as the SEM
micrograph in Fig. 2 (b) show.
It is planed to place semiconductor QDs or single molecules between the electrodes to measure their transport
characteristics. Furthermore samples with additional back gate electrode are in preparation which will provide an even
wider access to the electrical properties of nano-objects.

We present a technique to fabricate single-electron transistors (SETs) with silicon quantum dots (QDs) as conducting islands making use of a combination of self-assembly and self-alignment effects. Starting from an ultra-thin silicon-on-insulator (SOI) substrate we employ aminosilane as an adhesion agent to self-assemble gold colloidal particles in a sub-monolayer. These particles are then used as an etch mask for a CF₄ reactive ion etch (RIE) process in which the silicon is removed everywhere except below the gold colloids, yielding silicon QDs on a SiO₂ layer. A metal wire together with side gate electrodes is patterned by electron beam lithography (EBL) onto the QD-covered sample, and a nanometer-sized gap is created in these wires by a controlled electromigration process. Self-alignment of the evolving nano-electrodes with respect to the QDs is achieved, because the metal layer is locally dilated by the QDs resulting in a locally higher current density. Therefore the metal wires will preferentially break at the positions of the QDs. To obtain tunneling contacts the native oxide layer covering the silicon QDs is used as a tunneling barrier. Its thickness can be adjusted in a controlled manner by self-limiting thermal oxidation to obtain an accurate tunneling resistance. The devices are electrically characterized at liquid helium temperature and show clear Coulomb blockade behavior, Coulomb staircase features and the so-called Coulomb diamonds which are typical for SETs.

We present a technique to fabricate single-electron transistors (SETs) with silicon quantum dots (QDs) as conducting islands making use of a combination of self-assembly and self-alignment effects. Starting from an ultra-thin silicon-on-insulator (SOI) substrate we
employ self-assembled gold colloidal particles as an etch mask. Quantum dots are then fabricated by applying a CF₄ reactive ion etch
(RIE) process to remove the silicon layer everywhere except below the gold colloids. A 100-200 nm wide metal wire together with side
gate electrodes is patterned by electron beam lithography (EBL) onto the QD-covered sample and a nanometer-sized gap is created in these wires by a controlled electromigration process. The metal wires will preferentially break at the positions of the QDs, because the metal layer is dilated there resulting in a locally higher current density. This leads to a self-alignment effect of the evolving nano-electrodes with respect to the QDs. The native oxide layer covering the silicon QDs is used as a tunneling barrier. Its thickness can optionally be adjusted in a controlled manner by self-limiting thermal oxidation to obtain an accurate tunneling resistance. The devices are electrically characterized at liquid helium temperature and show clear Coulomb blockade behavior, Coulomb staircase features as well as the so-called Coulomb diamonds, typical for SETs.

We present a novel technique to fabricate single-electron transistors (SETs) with silicon quantum dots (QDs) as
conducting islands making use of a combination of self-assembly and self-alignment effects (for an overview of the
fabrication process, see Fig. 1). Starting from an ultra-thin silicon-on-insulator (SOI) substrate we employ aminosilane
molecules as an adhesion agent to self-assemble gold colloidal particles in a sub-monolayer [1]. These particles are then
used as an etch mask for a CF₄ reactive ion etch (RIE) process in which the silicon layer is removed everywhere except
below the gold colloids, yielding silicon QDs on a SiO₂ insulating layer. A metal wire together with symmetric side gate
electrodes is patterned by electron beam lithography (EBL) onto the QD-covered sample, and a nanometer-sized gap is
created in these wires by a controlled electromigration process [2]. Self-alignment of the evolving nano-electrodes with
respect to the QDs is achieved, because the metal layer is locally dilated by the QDs resulting in a locally higher current
density. Therefore the metal wires will preferentially break at the positions of the QDs. To obtain tunneling contacts the
native oxide layer covering the silicon QDs is used as a tunneling barrier. Its thickness can be adjusted in a controlled
manner by self-limiting thermal oxidation [3] to obtain an accurate tunneling resistance.
The devices are electrically characterized at liquid helium temperature by applying a source-drain voltage and
measuring the current. The I(V)-curves (Fig. 2) show clear Coulomb blockade behavior and Coulomb staircase features.
When the source-drain voltage is kept at a constant value and the gate voltage is varied, conductance oscillations
become visible. By collecting I_SD(V_SD)-traces for different gate voltages and calculating their numerical derivatives a so-
called stability diagram is obtained, exhibiting Coulomb diamonds which are typical for SETs.