We present a technique to fabricate single-electron transistors (SETs) with silicon quantum dots (QDs) as conducting islands making use of a combination of self-assembly and self-alignment effects. Starting from an ultra-thin silicon-on-insulator (SOI) substrate we employ aminosilane as an adhesion agent to self-assemble gold colloidal particles in a sub-monolayer. These particles are then used as an etch mask for a CF₄ reactive ion etch (RIE) process in which the silicon is removed everywhere except below the gold colloids, yielding silicon QDs on a SiO₂ layer. A metal wire together with side gate electrodes is patterned by electron beam lithography (EBL) onto the QD-covered sample, and a nanometer-sized gap is created in these wires by a controlled electromigration process. Self-alignment of the evolving nano-electrodes with respect to the QDs is achieved, because the metal layer is locally dilated by the QDs resulting in a locally higher current density. Therefore the metal wires will preferentially break at the positions of the QDs. To obtain tunneling contacts the native oxide layer covering the silicon QDs is used as a tunneling barrier. Its thickness can be adjusted in a controlled manner by self-limiting thermal oxidation to obtain an accurate tunneling resistance. The devices are electrically characterized at liquid helium temperature and show clear Coulomb blockade behavior, Coulomb staircase features and the so-called Coulomb diamonds which are typical for SETs.

We present a technique to fabricate single-electron transistors (SETs) with silicon quantum dots (QDs) as conducting islands making use of a combination of self-assembly and self-alignment effects. Starting from an ultra-thin silicon-on-insulator (SOI) substrate we
employ self-assembled gold colloidal particles as an etch mask. Quantum dots are then fabricated by applying a CF₄ reactive ion etch
(RIE) process to remove the silicon layer everywhere except below the gold colloids. A 100-200 nm wide metal wire together with side
gate electrodes is patterned by electron beam lithography (EBL) onto the QD-covered sample and a nanometer-sized gap is created in these wires by a controlled electromigration process. The metal wires will preferentially break at the positions of the QDs, because the metal layer is dilated there resulting in a locally higher current density. This leads to a self-alignment effect of the evolving nano-electrodes with respect to the QDs. The native oxide layer covering the silicon QDs is used as a tunneling barrier. Its thickness can optionally be adjusted in a controlled manner by self-limiting thermal oxidation to obtain an accurate tunneling resistance. The devices are electrically characterized at liquid helium temperature and show clear Coulomb blockade behavior, Coulomb staircase features as well as the so-called Coulomb diamonds, typical for SETs.

We present a novel technique to fabricate single-electron transistors (SETs) with silicon quantum dots (QDs) as
conducting islands making use of a combination of self-assembly and self-alignment effects (for an overview of the
fabrication process, see Fig. 1). Starting from an ultra-thin silicon-on-insulator (SOI) substrate we employ aminosilane
molecules as an adhesion agent to self-assemble gold colloidal particles in a sub-monolayer [1]. These particles are then
used as an etch mask for a CF₄ reactive ion etch (RIE) process in which the silicon layer is removed everywhere except
below the gold colloids, yielding silicon QDs on a SiO₂ insulating layer. A metal wire together with symmetric side gate
electrodes is patterned by electron beam lithography (EBL) onto the QD-covered sample, and a nanometer-sized gap is
created in these wires by a controlled electromigration process [2]. Self-alignment of the evolving nano-electrodes with
respect to the QDs is achieved, because the metal layer is locally dilated by the QDs resulting in a locally higher current
density. Therefore the metal wires will preferentially break at the positions of the QDs. To obtain tunneling contacts the
native oxide layer covering the silicon QDs is used as a tunneling barrier. Its thickness can be adjusted in a controlled
manner by self-limiting thermal oxidation [3] to obtain an accurate tunneling resistance.
The devices are electrically characterized at liquid helium temperature by applying a source-drain voltage and
measuring the current. The I(V)-curves (Fig. 2) show clear Coulomb blockade behavior and Coulomb staircase features.
When the source-drain voltage is kept at a constant value and the gate voltage is varied, conductance oscillations
become visible. By collecting I_SD(V_SD)-traces for different gate voltages and calculating their numerical derivatives a so-
called stability diagram is obtained, exhibiting Coulomb diamonds which are typical for SETs.

We present a technique to contact individual silicon quantum dots (QDs) by nano-­electrodes making use of a self-­alignment effect. Starting from an ultra thin silicon on insulator (SOI) substrate we employ self­-assembled gold colloidal particles as an etch mask. These particles are deposited onto the substrate using aminosilane [3­-(2­-aminoethylamino)propyltrimethoxysilane] as an adhesion agent yielding a sub­-monolayer sample coverage. The QDs are then fabricated by applying a CF₄ reactive ion etch (RIE) process to remove the silicon layer everywhere except below the gold colloids. Subsequently, the colloidal mask is removed by a wet chemical etch and 100-200 nm wide metal wires are patterned by electron beam lithography (EBL) onto the QD-­covered samples. A nanometer­-sized gap is created in these wires by a controlled electromigration process. The metal wires will preferentially break at the positions of the QDs, because the metal layer is dilated there resulting in a locally higher current density. This leads to a self­-alignment effect of the evolving nano­-electrodes with respect to the QDs. The native oxide of the silicon QDs is used as a tunneling barrier leading to a single­-electron device. The oxide thickness can be increased in a controlled manner by self­-limiting thermal oxidation to adjust the tunneling resistance. Finally, I(V)­-traces of these devices are collected at liquid helium temperature. They show clear Coulomb blockade behavior as well as Coulomb staircase features.

In this paper we present a novel approach to fabricate single-electron devices utilizing different self-organization and self-alignment effects. Silicon quantum dots (QDs) are obtained employing reactive ion etching (RIE) into a silicon-on-insulator (SOI) substrate with a self-assembled etch mask. Electrodes with nanometer separation are fabricated and aligned to the QDs by means of a controlled electromigration process. The tunneling rates of the devices are defined by the native oxide covering the silicon QDs and can be adjusted by self-limiting thermal oxidation. The devices show clear Coulomb blockade behavior as well as Coulomb staircase features. In some samples also a gate influence is present giving rise to Coulomb diamonds in the differential conductance diagram.